HomeSolid State SynthesisLow Resistivity Nanoscale Devices by Templated Electrochemistry

Low Resistivity Nanoscale Devices by Templated Electrochemistry

Mazin Maqableh, Madhukar Reddy, Bethanie Stadler

Department of Chemical Engineering and Materials Science, University of Minnesota, Minneapolis, Minnesota 55455, USA


In many technologies, performance requirements drive device dimensions below the scale of electron mean free paths (λe). This trend has increased scientific interest and technological importance of electrical resistivities at the nanoscale.1,16 Experimentally, transport properties have been measured in metallic nanostructures; however, contact design, corroded surfaces, grain boundary resistances, and scattering losses make measurements hard to interpret, especially for nanowires with exposed edges. Resistivity values can vary by several orders of magnitude for any given metal depending on fabrication and measurement techniques. Models of electron transport predict an order of magnitude higher resistivity for devices with 10 nm diameters due to sidewall scattering (λmetals~40 nm), even if roughness is only one atomic spacing.2 Enter templated electrochemically synthesized nanowires. Nearly bulk resistivities have been measured in 10 nm diameter metallic wires (200 nm long) that were synthesized inside anodic aluminum oxide (AAO) templates.1 This article explores AAO templates, followed by nanowire synthesis and measurement techniques that can be used to elucidate intrinsic resistivities of nanoscale metals.

Templates with Negligible Sidewall Roughness

Two-step anodization of aluminum (either Al foil (Aldrich Prod. No. 266574) or Al films on Si) is the best process for synthesizing reproducible, very small nanopores with high aspect ratios.3 This process involves applying a voltage to Al while it is submerged in either phosphoric (Aldrich Prod. No. 452289), oxalic (Aldrich Prod. No. 752835), or sulfuric acid (Aldrich Prod. No. 339741), depending on desired pore size. Although anodizing voltage has been the primary parameter used to reduce pore diameters from 250 down to 25 nm with a well-known linear dependence,4 nanopore diameter can be independent of voltage at the smallest sizes (Figure 1, page 42). Therefore, to achieve smaller diameters, other parameters such as electrolyte dilution and temperature have been explored. For example, electrolyte dilution can be optimized to get diameters smaller than 10 nm, but careful monitoring of the thermal conditions is important. Figure 1 shows scanning electron micrographs and histograms of nanopores made at different anodization voltages and electrolyte concentrations.1

Although these nanopores are excellent templates, nanowire devices discussed below can be electroplated into a variety nanoporous templates, including those being developed for bit patterned media (BPM).5 This is important for mass production of read sensors, RAM, or 3D nanoelectronics where long-range order will be necessary. Long-range order in alumina templates can be achieved by anodizing nanoimprinted Al,6 for example 74 nm diameter pores are shown in Figure 2. Although very expensive, imprint stamps with 8 to 18 nm features have been made industrially via large-scale lithography, which means ordered and small pores will be possible.7 It is important to note the expensive master stamps can be used to produce hundreds of wafers with 1012 electrochemically grown magnetic devices per square inch. In addition, daughter stamps from the e-beam masters can be produced in order to again multiply the number of sensors from each master by several orders of magnitude. Therefore, the cost per device will not be a barrier to implementation for industry, especially as e-beam lithography costs continue to decrease due to faster resists and writing software.

Nanoimprinted aluminum anodized using 160 V in 1% phosphoric acid at 0 °C.

Figure 2.Nanoimprinted aluminum anodized using 160 V in 1% phosphoric acid at 0 °C. Pores in the resulting oxide self-assembled to align with imprints (74±10-nm diameters). Adapted from Reference 1.

Synthesis of Nanowires

Watts-type electrochemical baths are the most common electrolytes for synthesizing nanowires inside AAO nanopores. These contain sulfates of the metals of interest, and boric acid to maintain pH at the working electrode, if required. A metal contact film, such as Ti/Cu or Cr/Au, is sputtered or evaporated onto one side of the AAO. This side of the sample is then isolated such that only the open pores are exposed to the electrolyte. Unlike the anodization process, the electrochemical deposition process usually requires a reference electrode placed near the working electrode (in this case, the AAO pores).

Although electrochemical deposition is a fairly standard technique, many functional metals, such as magnetostrictive alloys, involve rare earths or Ga, which oxidize easily and are, therefore, challenging to electroplate.8 For example, Figure 3A shows an Fe-Ga nanowire array grown under commonly employed conditions of agitation with a magnetic stirrer.9 The wire lengths exhibit a bimodal distribution, with large relative standard deviation. In many applications precise multilayer thicknesses are required, so rotating disk electrodes (RDE) are employed to create uniform hydrodynamic conditions near the template surface to control wire lengths (Figure 3B). Initial layers, such as Cu, can also act as nucleation sites for subsequent alloy deposition (Figure 3C). Pulsed deposition is another technique in which rest periods ensure the absence of non-uniform overlapping of diffusion fields (Figure 3D).10 In most cases, a combination of these strategies produces the most uniform results, as in FeGa nanowires shown in Figure 3.9

Diameter histograms of nanopores formed by anodization at various voltages

Figure 1.A–C) Diameter histograms of nanopores formed by anodization at various voltages and concentrations of H2SO4 at 1 °C, as shown in micrographs (D–F) and summarized in (G). Circled data points in (G) correspond to nanopores that were imaged using SEM as shown in the colored images. The pore size and distribution shown here were analyzed over large areas. Adapted from Reference 1.

Optimization of Fe-Ga nanowire growths.

Figure 3.Optimization of Fe-Ga nanowire growths. Statistical analysis of nanowire lengths is superimposed on the corresponding SEM image. The schematics represent the diffusion profiles existing during growth in each case. A) Bimodal distribution obtained when the solution was agitated using a magnetic stirrer; B) after use of RDE-template at a rotation rate of 1,800 rpm; C) after use of Cu seed layer in addition to RDE-template; and D) use of pulse deposition in addition to Cu seed layer and RDE-template. Identical growth conditions including deposition potential, solution concentrations, and time of deposition were used. Adapted from Reference 9.

Measuring Resistivity of 10 nm Nanowires

For statistical analysis of resistivities of 10 nm diameter nanowires, Aucoated AFM tips are used with various contact forces such that 1–3 wires are contacted.11 A histogram of such resistance measurements for primarily copper nanowires is shown in Figure 4.1 In the first ten measurements, single nanowires were contacted. All possible combinations of pairs of these 10 single nanowire measurements are shown next to the cluster of measurements in which 2 wires were contacted. Results for all 120 combinations of 3 single wires were compared to the next grouping of measured resistance values. These results indicate the first 10 measurements were those of single wires with resistances of 119.8±21.6 Ω. The average and distribution corresponds to 3.2 times the resistivity of bulk copper (ρo), or 5.4 μΩ⋅cm for the average diameter (10.6±1.7 nm) determined from micrographs such as Figure 1B using NIH freeware. The high resistance "tail" of the data shown in Figure 4 is expected for an inverse Gaussian distribution that arises from resistances of nanowires with Gaussian distributions in diameters and, therefore, in areas (Figure 1B). This occurs due to the inverse relationship between resistance and area, R = ρ /A where was 190 nm for all of the wires.

Resistance histogram of 10-nm nanowires measured (purple) while inside the AAO matrix.

Figure 4.Resistance histogram of 10-nm nanowires measured (purple) while inside the AAO matrix. The measured groupings were separated by resistance gaps as 1, 2, or 3 wires were contacted. Blue points correspond to the 45 combinations of any two measurements of the individual nanowires. Green points correspond to all 120 possible combinations of any three individual nanowires. Adapted from Reference 1.

The International Technology Roadmap for Semiconductors (ITRS) has identified the "size effect" of increased resistivity (ρ) in nanostructures as a Grand Challenge to continued scaling of electronics. This increase in resistivity compared to bulk resistivity (ρo) is usually attributed to electron scattering from surfaces that can be approximated using the Fuchs-Sondheimer (FS) theory12,13 for cylindrical wires:

Fuchs-Sondheimer (FS) theory12,13 for cylindrical wires

where κ = D/λe, D is the wire diameter, λe is the mean free path of the electrons (39 nm for bulk Cu), and ρ is a constant (0-1) that depends on the type of electron reflection off the sample surfaces (from diffuse to specular). Most horizontally patterned nanowires from electroplated Cu films are even more resistive than this approximation predicts because grain boundaries etch preferentially, so the edges are rough after the nanowire is defined. Therefore, resistivities comparable to nanowires synthesized in AAO are only obtained with an order of magnitude larger cross sectional area.14 Using the FS approximation, diffuse scattering at the sidewalls of 10 nm diameter nanowires predicts resistivities 19% higher than the measured resistivities of nanowires synthesized in AAO.

These resistances are higher than predicted by Equation 1 because the approximation underestimates the size effect compared to exact solutions of the FS theory.15 This result has also been confirmed analytically and numerically using an atomistic tight-binding approach where resistance (R) was calculated as a function of wire length to determine λe using

FS theory

where h and e are Planck′s constant and electron charge, M is the number of conducting channels whose subbands cross the Fermi level, and Tave is the average transmission probability.2 This model predicted one atomic monolayer roughness would cause an order of magnitude higher resistivities for 10 nm diameter nanowires inside alumina compared to bulk. However, calculated resistivity is 200% higher than measured resistivities for AAO-template-synthesized nanowires, which leads us to conclude the AAO synthesized nanowires have very smooth sidewalls. Therefore, nanowires have great promise for device applications as low resistivity interconnects, random access memory,17-29 and readheads.20


Templated electrochemistry allows the synthesis of nanodevices with very smooth sidewalls. This could provide a solution to the ITRS Grand Challenge calling for low resistivity interconnects at the nanoscale by mitigating the "size effect." In addition, devices in AAO templates can be synthesized in arrays with densities of 2 Tbit/in2, a density usually reserved for hard drive media to date. Aspect ratios up to 10,000× are possible, which opens the possibility of better performance and even 3D devices. Given the extensive knowledge available for the synthesis of such devices, a wide range of applications should begin to emerge in the near future.



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